library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
USE ieee.numeric_std.all;

entity selector_fraccion is
	port(
		 a, b	: in std_logic_vector (7 downto 0);
		 sel	: in std_logic;
		 out1, out2	: out std_logic_vector(7 downto 0)
		 );
end selector_fraccion;

architecture arch_selector_fraccion of selector_fraccion is
begin
	process (sel)
	begin
		if (sel = '0') then
			out1 <= b;
			out2 <= a;
		else
			out1 <= a;
			out2 <= b;
		end if;
	end process;
end arch_selector_fraccion;
